One of the main problems in digital transmission between far (satellite earth station) or near (telephone exchange subscriber) points is transmitter and receiver synchronization.
This operation is typical of all receiving devices in order to accurately estimate the electric levels of the signal received. In fact, the knowledge of the signaling period limits, i.e. the period where a single elementary information is transmitted, makes it possible to determine the optimum sampling instant. This is the instant of minimal effects of noise and distortions introduced by the transmission channel and of maximum probability of a correct estimate of the symbol received.
This problem has been solved generally in three modes:
(a) to obtain coincidence between the signaling period of the signal received and the locally generated frequency reference signal using extremely stable generators at both transmitter and receiver. For this purpose, selected crystals, rubidium or cesium oscillators or expensive masers can be used for example. PA1 (b) to use, as in case (a), less expensive generators and more frequent manual settings. This introduces high costs of specialized staff and in same cases difficulties because of equipment location (mountains, submarine, satellite repeaters). PA1 (c) to use devices which automatically correct for frequent drift. PA1 effects integration with comparatively few logic gates; PA1 is characterized by high jitter reduction; PA1 has high resolution and speed in estimating the phase of the signal received; PA1 can be used even with inexpensive frequency references (as distinct from selected crystals or ceramic oscillators); PA1 requires no initial or periodic settings; and PA1 can be used in different applications through a suitable parameter dimensioning. PA1 a set of comparators, their number being one less than the electric levels of serial flow, which receives as input this flow and emits at an output a signal indicating the occurred internal threshold crossing and at another output a signal indicating the direction of threshold crossing; PA1 a first set of flip-flops in number being equal twice that of said comparators, which stores the signals emitted by the comparators; PA1 a first OR gate, connected to the outputs of the flip-flops which store the signals indicating the occurred crossing of comparator thresholds; PA1 a first counter, which is enabled to count a clock signal by the signal emitted by the first OR gate and is reset by the signal emitted by a first delay cell, which resets also the set of flip-flops after the reception of the over-flow signal emitted by the first counter; PA1 a decoder, which is enabled by the overflow signal emitted by the first counter and emits for each output, a signal identifying the type of level transition, which occurred in the serial data flow, the detection being carried out on the basis of the signals sent by the set of flip-flops; PA1 a second counter, which counts the clock signal; PA1 a first register, enabled by the signal sent by the first OR gate in order to store the value counted by the second counter and to transfer it at its output after the transition of the signal sent by the first delay cell; PA1 a set of accumulators in number being equal to the number of different types of transitions to be taken into examination, which are enabled one-by-one by the signals sent by a first set of AND gates in order to accumulate the signals sent by the first register and emit the result of the accumulation after the signal sent by a set of counters; PA1 a set of registers, which stores the results sent by the accumulators, duly divided by the number M of accumulation operations disregarding the least significant log.sub.2 M bits, when the signal sent by a first AND gate is present, and emits them after the signals supplied by the decoder through a set of OR gates or directly; PA1 a set of counters each counting the number of transitions of a type, which receives from the decoder through a second set of AND gates, enabled by the signals sent by a second set of flip-flops, which stores the overflow values sent by the same set of counters; PA1 the first gate which receives the signals emitted by the second set of flip-flops; PA1 the first set of AND gates, each receiving a signal emitted by the decoder and a signal emitted by the second set of flip-flops; PA1 a second AND gate which receives at an input the signal emitted by the first AND gate and at the other input the same signal delayed by a second delay cell, and emits a pulse which sends to the set of OR gates, either directly or through a set of delays cells and to a third delay cell; PA1 an adder, which is enabled by the signal emitted by the third delay cell to add the signals sent by the set of registers at successive instants; PA1 a first subtractor, enabled by the signal emitted by the second delay cell which generates the difference between the signals emitted by one of said set of registers and the first register; PA1 an up-down counter, which counts upward or downward according to the difference sign supplied by the first subtractor and is reset when the maximum or minimum counting value is reached, the resetting signals being used to change of one more or less unit the counting module of the second counter; and PA1 a second subtractor enabled by the signal emitted by the second delay cell which generates the difference between the signal emitted by the first subtractor, whose least significant bit is disregarded to carryout a binary division by two, and the signal emitted by the second counter, the signal emitted by the second subtractor being frequency and phase locked with the incoming data serial flow.
Information on the signaling period of the signal transmitted is in this case acquired by the receiver, which extracts it from data flow received, remedying both the distortion introduced by the channel and the frequency and phase differences of remote and local timing generators.
Once having obtained this information, a signal duly placed within the signaling period can be generated in order to acquire the logic level of the signal received.
Obviously, this is the least expensive and most versatile mode, as it easily adapts to different applications.
To date, a phase-locked loop, or PLL, has generally been used; it consists of a phase comparator, a filter and a controlled oscillator (for example a VCO=Voltage Controlled Oscillator).
The phase comparator determines the phase differences between the input signal and the local reference; the phase error detected is filtered so as to reduce the noise, and is sent to the controlled oscillator, which adapts the frequency of the locally generated signal accordingly.
These three components were implemented in the past with analog techniques; for example, the phase comparator can be implemented with a balanced mixer, the filter with a simple RC low-pass circuit and the VCO with a varicap (voltage controlled capacitor) which varies the resonance frequency of a tuned circuit when the voltage applied to its terminals varies.
Recently, the number of digital devices introduced into PLL's have been increased. At first, a sample-and-hold circuit was placed after the filter, so as to use a digital VCO. Then, the phase comparator and next the filter became digital, thus obtaining a fully digital PLL, that is a DPLL (digital phase locked loop).
In a DPLL implementation, the phase error is determined by estimating the lead or delay of the signal emitted by the local generator with respect to the signal emitted by the remote generator: this estimate is carried out each time and the signal received exceeds a preestablished electric threshold.
The error signal, proportional in amplitude and sign to the phase difference, is filtered and used for the necessary corrections of the local generator.
One of the main problems presented by these types of DPLL's depends on the synchronism loss in the presence of a low content of level transitions in the signal received, in particular in the case of long sequences of identical symbols. These disadvantages are overcome by the use of line coders, which increase the transition content and then the information on phase behavior.
Nevertheless, a high content of transitions implies an accurate filtering of the error estimated in order to obtain a reliable value of the signal to be used for the corrections of the local generator. This makes it possible to minimize the effects of the random variations of zero crossings (jitter). Anyway, filtering requires complex devices and algorithms, to the detriment of convergence speed and integration easiness.